Silicon substrates suffer from two problems that make it more difficult to process, package, and operate semiconductor die packages. The first is expanding when heated at a rate that is different from the rate of expansion of other related parts such as package substrates. The second is warping when heated. This occurs to silicon substrates that have metal upper layers because the silicon expands at a different rate from the metal. These problems occur for standard flip-chip packaging, embedded dies within substrate technologies, and other types of semiconductor substrates.
Results of these thermal effects include assembly stress on both solder joints and ILDs (Inter-Layer Dielectric) leading to failure when a silicon substrate is attached to a package substrate. FLI (First Level Interconnect) solder joint and ILD reliability can be affected. During reliability stress testing and product use, the temperature of a die may change from as low as −55° C. to as high as 125° C. The thermal expansion of the die relative to the package substrate stresses the solder joints and the ILD which may lead to product failure. FLI and SLI (Second Level Interconnect) SJR (Solder Joint Reliability) are both affected for standard flip-chip packaging.
Die warpage affects embedding, solder reflow, and thermal compression bonding. Because the Silicon has numerous layers of copper built up on one side, the CTE (Coefficient of Thermal Expansion) difference between the silicon and copper creates a bending moment which leads to die warpage. Consequently, standard PnP (Pick and Place) and solder reflow processes can be impacted by non-connect opens, solder bridging and misalignment. This impact is increased as the solder bump pitch shrinks, as the chip area increases, and when both happen in combination because in some areas the substrate solder does not contact or wet the chip bump. Furthermore, the warpage of the die requires a chip holder to exert a strong vacuum on the chip to ensure the die is held flat. Once the chip is released, die warpage can influence solder joints particularly if the chip is released prior to solder solidification. Furthermore, strong adhesives are needed to hold a die flat on an embedding panel once placed to prevent the die from curling up. Often non-conductive, epoxies are used which then either limit the thermal conduction through the die back-side or require etching in order to enable a thermal conduction solution.
Embedded die and package stress caused by warpage and CTE mismatch can also cause failures. The CTE mismatch between the silicon and package build up layers, typically made of copper and dielectric, leads to thermal stresses on the ILD and the vias in the die. This is exacerbated during temperature cycling and can lead to via pump out and ILD cracking.
CTE mismatches are not limited to substrates based on silicon and silicon dioxide. Similar problems occur with other types of substrates such as inorganic, ceramic, glass, silicon-on-insulator (SOI), germanium, III-IV attached to organic and organic/inorganic composite substrates.